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GS3 · Technology

Design Linked Incentive scheme: 24 chip design projects

1 min readSemiconductors
Battle IAS current affairs title card: Design Linked Incentive scheme: 24 chip design projects (GS3 · Technology, 4 January 2026)

What happened

  • MeitY’s Design Linked Incentive scheme under the Semicon India Programme supports 24 chip design projects [PIB].
  • They have produced 16 tape-outs, 6 ASIC chips and 10 patents, engaged over 1,000 engineers and leveraged over three times private investment [PIB].

Background

  • Chip design contributes up to 50% of value addition in semiconductors [PIB].

Why it matters

  • Fabs get the headlines, but design is where India already has talent. DLI is the cheaper lever.

How to use this in Mains

GS-III Science and technology: IT, computers, robotics, indigenisation

  1. As per PIB (2026-01-04): meitY's Design Linked Incentive scheme under the Semicon India Programme supports 24 chip design projects.
  2. Fabs get the headlines, but design is where India already has talent. DLI is the cheaper lever.
Quotable data point

They have produced 16 tape-outs, 6 ASIC chips and 10 patents, engaged over 1,000 engineers and leveraged over three times private investment.

PIB: Design Linked Incentive Scheme, 4 Jan 2026

Exam angle

UPSC

Prelims: DLI, tape-out.

Practice MCQs

Original practice questions (not PYQs).

Practice · UPSC

DLI scheme is part of

Answer (b) & explanation

PIB.

Go deeper

ExplainerSemiconductors and India: What Chips Are, the Global Value Chain, India Semiconductor Mission, New Fabs and Packaging Units, Challenges and the Way Ahead (UPSC Notes + PYQs)

Official source: PIB: Design Linked Incentive Scheme, 4 Jan 2026

facts from cited sources only; faculty review pending